# Multiplication by Halving and Doubling in AARCH64 Assembly

While multiplication is defined in the context of repeated addition, implementing it that way algorithmically is not nearly as efficient as some other approaches. One algorithm for multiplication that is an order of magnitude faster is to halve one number while doubling the other. I gave myself the challenge of implementing this algorithm in AARCH64 Assembly, and it was not too hard.

This exercise allowed me to work through a few operations.

• In order to double a number, you shift its bits left.
• In order to cut it in half, you shift it right.
• In order to check if a number is negative, you perform a logical and with the most significant bit.
• In order to reverse the sign of a number, you perform an exclusive or (eor) on the bits.
• In order to check if a number is odd or even, you perform a logical and with the least significant bit

Here’s the code. I used the debug.s file as presented by Stephen Smith in “Programming with 64-bit ARM Assembly Language.” The main section of the code is a series of unit tests that show the algorithm works for various ases of positive, negative, and zero value operands.